1. Field of the Invention
This invention applies to the field of integrated circuits (IC) known as differential receivers. It is specific to IC devices used for receiving digital data that is transmitted over long transmission lines. The field includes all bipolar differential receivers and all insulated gate field effect transistor (IGFET) differential receivers, including CMOS circuits.
2. Background Information
When digital data signals that contain long runs of either ones or zeroes are sent over a long transmission line, the edges that correspond to the data transitions (0-1 or 1-0) become severely distorted by the bandwidth limitation and the frequency dispersion of the transmission line. This phenomenon, known as inter-symbol interference (ISI), moves the transition edges associated with these long runs from their ideal clock positions thus interfering with the correct recovery of data by the receiver.
The prior art in differential receivers does not provide a solution to this problem that is implemented at the receiver. Lacking a solution at the receivers, data transmission system designers have taken a system approach to mitigate the problem of ISI. In the systems approach, designers have used a technique called xe2x80x9cpre-emphasisxe2x80x9d in the driver circuit. For example, the transmission line driver asserts a 1-0 transition level that is stronger than a sustained 1-1 data level, and it asserts a 0-1 transition level that is stronger than a sustained 0-0 data level. These emphasized transitions tend to compensate for the anticipated distortion of the pulses that follow long high or long low bit sequences. The xe2x80x9cpre-emphasisxe2x80x9d system solution to the ISI problem complicates transmission system designs. Designers prefer a solution that is implemented at the differential receiver for use in systems where they have no control over the driver choice. As data transmission rates rise, ISI becomes even more problematic since high-speed circuits have decreased margins for timing errors. In these higher speed systems, both the driver and the receiver must be capable of addressing the ISI problem.
ISI creates data errors at the receiver by causing pulse width distortion that shifts the transition edges for the bits at the end of a long run of either ones or zeroes. FIG. 1 illustrates an oscilloscope plot of a differential xe2x80x9c1111101010xe2x80x9d bit pattern after transmission through 20 meters of cable. The prior art differential receiver generates output pulse transitions at the points where the two waveforms cross. Ideally, these data transitions should occur every 941 picoseconds (ps). However, because of ISI, the xe2x80x9c11111xe2x80x9d run pattern has a length of 4950 ps instead of the ideal value of 4705 ps. In addition, the xe2x80x9c01010xe2x80x9d pulses following the xe2x80x9c11111xe2x80x9d run also have distorted widths of xcx9c625 ps, xcx9c1200 ps, xcx9c750 ps, xcx9c1150 ps and xcx9c750 ps, respectively, instead of the ideal value of 941 ps. Prior art differential receivers would produce output pulses with these same pulse width distortions.
FIG. 2 illustrates the prior art in digital differential receivers. The circuit consists of two matched bipolar transistors (or IGFET), T1 and T1xe2x80x2, connected in common at their emitters (or sources) to a current source IT. The collector (or drain) of each transistor is connected to the supply voltage Vcc through matched load resistors RL and RLxe2x80x2. The differential inputs va and vb are applied at the base (or gate) of each transistor. The differential outputs voa and vob are taken from the collector (or drain) of each transistor. Each time that the differential signal reaches zero, a transition occurs between the high and the low states of each of the outputs voa and vob relative to supply ground. If va is greater than vb as the differential input approaches zero then the transition is in one direction. When va is less than vb approaching a zero then the transition is in the opposite direction. The polarity of a transition at voa is the opposite of that at vob.
The invention provides an advancement of the art in differential receiver integrated circuits because it implements rejection of ISI at the receiver. Prior art differential receivers generate output pulses whose widths are affected by the preceding data. The ISI-rejecting differential receiver does not, so high levels of ISI in the input signal are rejected. For many digital data transmission systems this new type of differential receiver IC can provide sufficient ISI rejection to eliminate the need for xe2x80x9cpre-emphasisxe2x80x9d at the driver. It also enables still higher data transmission speeds since it allows the mitigating technique of xe2x80x9cdriver pre-emphasisxe2x80x9d to be combined with ISI rejection at the receiver. The invention applies to all bipolar (n-p-n or p-n-p) technologies and to all IGFET (p-channel or n-channel) technologies, including CMOS.
A primary differential transistor pair is augmented with a secondary (weaker) transistor pair and a pair of filter networks. These components combine the signals from both sides of the difference circuit to create a high pass xe2x80x9cshelfxe2x80x9d filter between the differential input and the outputs. At low frequencies, the dual-pair network reduces the gain of the differential amplifier. At high frequencies, the gains of the two pairs add. The break frequency for the gain change is set by an RC time constant of the network. The ratio of input device sizes and resistor ratios in the network determine the difference between the minimum gain and the maximum gain.